1. Field of the Invention
The present invention relates to integrated circuits of the type that use resistor strings for interpolation between two points of differing potential.
2. Prior Art
Many applications require linear interpolation between two points of differing potential where the interpolated point is programmable. The simplest way to implement this is to fix a string of resistive elements between two potentials, with switched taps at every node, as shown on FIG. 1. Each resistive element can be of any value, but for linear interpolation all elements must be nominally identical. Usually, and for the purposes of further discussion, the resistive element is an ohmic resistor.
When implementing such a structure on an integrated circuit, non-idealities in semiconductor processing lead to non-linearities in a nominally linear set of resistors. The measures of non-linearity to be considered are Differential Non-Linearity (DNL), defined as the deviation from the ideal voltage difference between tap n and tap n+1, and Integral Non-Linearity (INL), defined as the deviation of the voltage at tap n from an ideal voltage given by:       V    IDEAL    =                    (                                            V              H                        -                          V              L                                N                )            ⁢      n        +          V      L      
where VH and VL are the higher and lower of the voltages to be interpolated between, N is the total number of taps and n is the tap under consideration (1xe2x89xa6nxe2x89xa6N, numbering the taps from 1 to N).
The sources of INL and DNL in such an integrated system can be generalized as the random mismatch between two adjacent resistors due to process imperfections, contact resistance, mask tolerances, diffraction effects, etc., and the macro-scale (i.e.,  greater than  greater than than the dimensions of an individual resistor) resistivity gradients across the structure.
The present invention concerns a novel way of arranging such a set of resistors so as to minimize INL and also a way of switching between voltage taps which least perturbs the voltages on the resistor chain. This is very important in low output glitch designs and also when more than one voltage tap is simultaneously selected from the same set of resistors.
Enhanced linearity, low switching perturbation resistor string matrices. The resistor strings are arranged in an array of a plurality of rows of resistive elements and electrically arranged with rows equally spaced above and below the physical centerline of the array being coupled together in an opposite sense. Preferably also physically adjacent rows are equally spaced from the center of the electrical order of rows. This connection prevents accumulation of errors due to vertical and horizontal resistance gradients over the array. Also node selection by controlling node select transistors coupled to column select lines to select one node in each row, and also controlling row select transistors to select the row of the desired node minimizes settling time after a tap change by inducing equal and opposite voltage changes at points close together along the resistor string, whether in the array of the present invention or in the snake configuration.